The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits.
A variety of techniques are used to stack integrated circuits. Some techniques stack circuits encapsulated in special packages, while other methods stack conventional integrated circuit (IC) packages. Some techniques rely principally on the IC leads to create the stack and interconnect the constituent ICs. In other methods, structures such as rails are employed create the stack and interconnect the ICs. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect the constituent IC elements of the stack.
In some stack configurations, printed circuit board supports an interconnection network employed to provide inter-element connectivity. For example, in U.S. Pat. No. Re. 36,916 to Moshayedi, a technique is described for creating a multi-chip module that purportedly uses PCB sideboards to mount an assembly of surface-mount packaged chips to the main or motherboard. The constituent ICs are interconnected on their lead-emergent sides through printed circuit boards (PCBs) oriented vertically to a carrier or motherboard connected to connective sites along the bottom edge of the PCBs. Other systems also purport to use sideboard structures. For example, Japanese Patent Laid-open Publication No. Hei 6-77644 discloses vertical PCBs used as sideboards to interconnect packaged circuit elements of the stack.
Others have stacked integrated circuits without casings or carrier plates. Electrical conductors are provided at the edges of the semiconductor bodies and extended perpendicularly to the planes of the circuit bodies. Such a system is shown in U.S. Pat. No. 3,746,934 to Stein.
Still others have stacked packaged circuits using interconnection packages similar to the packages within which the integrated circuits of the stack are contained to appropriately route functionally similar terminal leads in non-corresponding lead positions. An example is found in U.S. Pat. No. 4,398,235 to Lutz et al. Simple piggyback stacking of DIPs has been shown in U.S. Pat. No. 4,521,828 to Fanning.
Some more recent methods have employed rail-like structures to provide interconnection and structural integrity to the aggregated stack. The rails are either discrete elements that are added to the structure or are crafted from specific orientations of the leads of the constituent circuit packages. For example, in U.S. Pat. No. 5,266,834 to Nishi et al., one depicted embodiment illustrates a stack created by selective orientation of the leads of particularly configured stack elements, while in U.S. Pat. No. 5,343,075 to Nishino, a stack of semiconductor devices is created with contact plates having connective lines on inner surfaces to connect the elements of the stack.
Other sophisticated techniques have been recently developed for stacking integrated circuits. One recent technique developed by the assignee of the present invention interconnects conventionally packaged ICs with a flexible circuit disposed between stack elements. The flexible circuit includes an array of flexible conductors supported by insulating sheets. Terminal portions of the flexible conductors are bent and positioned to interconnect appropriate leads of respective upper and lower IC packages.
One of the more widely employed circuit packages used in high density circuit module stacks is the thin small outline package commonly know as the xe2x80x9cTSOPxe2x80x9d. A variety of circuits are available in TSOP packages. For example, a TSOP may contain a double data rate (xe2x80x9cDDRxe2x80x9d) memory circuit or a single data rate (xe2x80x9cSDRxe2x80x9d) memory circuit. DDR and SDR memory circuits in TSOP packages are generally available in 4-bit, 8-bit, and 16-bit wide data path configurations.
As control and embedded applications migrate to wider data path microprocessors and 64-bit microprocessors move into server and other general purpose uses, memory channels with wider data paths are more frequently found. Yet, common-sized TSOPs such as 66-pin and 54-pin packages are not commonly available in 32-bit data path configurations. Therefore, stacked modules that employ TSOPs have not been available in reliable configurations for 32-bit and other wide data path applications.
What is needed, therefore, is a technique and system for stacking integrated circuits that provides a thermally efficient, robust structure that provides a wider data path for the stacked module than present in the ICs of the module constituent while providing reliable performance with readily understood construction.
The present invention provides a system and method for selectively stacking and interconnecting individual integrated circuit devices that have a data path of n-bits to create a high-density integrated circuit module adapted for a data path of greater than n-bits. It is principally devised for use with memory circuits, but the invention can be employed to advantage with any type of packaged and leaded integrated circuit where area conservation and use of duplicative circuitry are present considerations and there is a need for the module to express a data path wider than that of the constituent elements of the stack.
Integrated circuits are vertically stacked one above the other. In a preferred embodiment, the stack consists of two packaged integrated memory circuits, but alternative embodiments may employ greater numbers of ICs, whether those ICs are memory or other circuits.
In a stacked module created in accordance with a preferred embodiment of the present invention, the constituent IC elements act in concert to provide an assembly of memory capacity approximately equal to the sum of the capacities of the ICs that constitute the assembly. Where the constituent IC elements have a data path of n-bits in width, a module devised in accordance with a preferred embodiment of the present invention presents a data path 2n-bits wide. The module may be used in a variety of applications such as, for example, individually as mounted on a circuit or motherboard or a plurality of modules devised in accordance with the present invention may be mounted on a dual-in-line (DIMM) board.
In a preferred embodiment, an interconnection frame comprised of printed circuit board material is disposed about two similarly oriented ICs to provide interconnectivity for the constituent ICs. Along lengths of the interconnection frame, there are pads for connection with the constituent ICs and a set of module connection pads through which connection of the module to a carrier or motherboard or other application environment is made. An array of clip-leads or other connectors are appended to the module connection pads to provide lead-like structures for connection of the module to its operating environment. Through the interconnection frame, adjacent ICs of the stack are interconnected. In a two-high stack, address lines of the constituent ICs are interconnected, while the data lines of the respective ICs are concatenated to double the data path width of the stack relative to the data path width of the constituent ICs. Other embodiments may combine the data paths of the constituent ICs either by concatenation or other arrangements to create a larger module data path than is presented by the constituent ICs of the module.
In an alternative preferred embodiment, two facially juxtaposed TSOP ICs are surface mounted to an interconnection body laterally positioned between the ICs. The interconnection body has IC connection pads and a set of module connection pads for connection of the module to a mother or carrier board. The interconnection body has a network of connections that interconnects the address lines of the constituent ICs and concatenates the data lines to double the data path width of the stack relative to the data path width of the ICs from which the stack is composed. An array of clip-leads or other connectors is appended to the module connection pads to provide lead-like structures for connection of the module to its operating environment.